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A RTCA-DO-254 Compliant development technique for helping the Design of notable hard IP Cores

via Patricia Lira1,2 and Edna Barros11 Federal college of Pernambuco, Informatics middle - UFPE2 Centro de Tecnologias Estratégicas do Nordeste – CETENERecife, Brazil


The increasing structural complexity and the reducing dimension of built-in circuits, linked to the discount on design time, demands that the hardware fashion designer makes use of a extremely smartly planned design flow to gain high pleasant IP-cores.

With expanding demand on extra complicated IP-cores, mechanisms for guaranteeing the design quality are being standardized and need to be protected within the design circulation. The DO-254 ordinary is an example of such standardization for airborne systems.

during this context, the availability of a development method for hardware is a pretty good help for having described a set of ordered steps for designing excessive excellent digital methods. The ipPROCESS is a manner for designing super soft IP-cores that has supported the design of IP-cores from its specification unless its prototyping in FPGA.  besides the fact that children, nice regular for digital programs comprises also the prototyping as ASIC.

This paper proposes an improvement of the present ipPROCESS version, which includes all flows and activities for designing terrific tough-IP-cores together with synthesis, examine and layout technology. For this intention, three news disciplines had been included within the ipPROCESS; the disciplines for Synthesis, for test and for lower back-end. every self-discipline comprises the workflow of all activities, Roles and Artifacts. For validating this new ipPROCESS unencumber a liquid crystal display controller has been designed from this specification unless ASIC prototyping. the usage of the ipPROCESS for directing the synthesis, verify and layout design has decreased the design time in 50%. moreover the remaining edition of ipPROCESS is 100% compliant with the necessities of DO-252 usual which makes using the ipPROCESS very enjoyable for assisting the design of IP-cores that have to be licensed according the DO-254 ordinary.


The complexity of the built-in circuit techniques and the enabling integration applied sciences enable to combine the whole system into a single chip, called SoC (gadget-on-Chip). however, because of the reduced time-to-market, IC design methodologies are using reusable components previously designed, the IP-cores, as an alternative to facilitate the design of a fancy and comprehensive device.

additionally, the expanding structural complexity and the decreasing size of integrated circuits, associated with the reduction on building time, demands that the hardware fashion designer uses a very neatly planned design circulation. Designers have, for this reason, increasingly adhered to inflexible, speedy and consistent design methodologies which are extra amenable to design automation.

during this context, the usage of a building manner looks to be a very good approach to outline the design move as a collection of neatly defined and ordered steps to guarantee the design excessive best integrated circuits.

As outlined, the current edition ipPROCESS supports the design of sentimental IP-cores with prototyping in FPGA. This work proposes a new version of the ipPROCESS that supports the activities of synthesis, look at various and layout generation for ASIC prototyping of tough IP-cores.

2. linked WORKS

during this section we briefly talk about some related works in the area of technique building for software design and the DO-254 ordinary for designing important programs in hardware.

The Rational Unified procedure [1][2], RUP is a  system framework developed by means of the Rational software organisation, from IBM, in 2003. The RUP items an iterative view of decent practices to application building and venture management, which is getting used in thousands tasks worldwide.

RUP consists for six engineering disciplines   modeling, necessities, evaluation & design, implementation, verify and deployment - prepared alongside 4 venture lifecycle phases – concept, elaboration, development and transition. A utility team that desires to boost a undertaking in keeping with RUP can customize the acceptable system aspects that meet their needs.

probably the most RUP advantages is to be a manner iterative and incremental. The iterative manner helps to control the alterations on the challenge necessities, while the incremental formulation aids the mission crew to reveal outdated equipment version to the client and avoids an implementation that diverge from the actual customer needs.

an extra linked approach in the enviornment of software building is the extreme Programming (XP) manner [3][4]. It turned into created via Kent Beck, in line with his work on the Chrysler comprehensive Compensation equipment payroll mission[5].  Some development practices purposed with the aid of XP are pair programming, test-driven development, continual integration and a construction divided in small releases.

RTCA DO-254[6], Design Assurance counsel for Airborne electronic Hardware, is a standard used for design assurance of airborne electronic hardware. The document classifies the design in 5 design assurance stages A-E, through which the failures in tasks with degree A represents the larger security have an impact on.

three. THE ipPROCESS development system

The ipPROCESS[7][8]  is a method to advance smooth and difficult IP-cores from its specification until its FPGA and ASIC prototyping. it's at present on the edition 3.0 and its leading aim is the building of notable IP-cores that meets the design constraints. To achieve this, the ipPROCESS gives a disciplined method to assigning tasks and tasks inside a construction firm and is in line with utility Engineering ideas, supported with the aid of tactics such as RUP (Rational Unified technique) [1] and XP (extreme Programming) [2]

figure 1 gifts the key ideas to keep in mind the normal constitution of this technique and the way the points as correlated. 

figure 1. ipPROCESS Key concepts.

The conception of discipline has been included from RUP, through which the self-discipline is described as a collection of activities related with an “area of subject” of the project. It consists of a group of discipline workflows that describes a series of actions with begin and end.

each endeavor is a work unit executed for a in charge that represents a job in the venture. The undertaking has a set of ordered steps and a collection of inputs and outputs artifacts. An endeavor will also be supported by some work guidelines and cautioned tools. The desk 1 suggests an instance of the exercise template.

desk 1. endeavor template.

Roles are composed by using a set of tasks and conduct that a person has to assign to execute some activities in the context of the development firm. It can also be represented by way of a single or a gaggle of person.

Artifacts are a piece manufactured from the challenge that has as in charge the position associated to the pastime that generated it.

figure 2 shows the four ipPROCESS phases: theory, architecture, RTL design and prototyping. each part is practically a span of time between two fundamental milestones. At each phase-conclusion, an assessment is carried out to determine whether the ambitions of the section were met. A adequate assessment allows for the task to move to the next phase.

determine 2. ipProcess phases.

determine 3 suggests the proposed ipPROCESS Lifecycle Diagram. It indicates the disciplines and the effort completed in each discipline along the design’s phases and iterations.

The proposed ipPROCESS is composed via 8 disciplines that support the design of an IP-core ranging from requirements seize except the prototyping in FPGA or as ASIC.

The disciplines are described in terms of activities (that neighborhood related tasks), workflows, artifacts, and roles, happening during this order:

figure three. ipPROCESS Lifecycle Diagram.

  • necessities: contains 5 actions, 7 artifacts, 5 templates, for establishing and keeping settlement with the shoppers on what the IP-core should still do.
  • analysis & Design: includes 3 activities, eight artifacts, three templates for transforming the requirements into a design of the IP-core.
  • RTL Implementation: comprises 6 activities, 4 artifacts and, 2 templates and 1 script for enforcing the accessories, based on the IP-core structure in some HDL.
  • useful Verification: comprises 8 activities, 7 artifacts, 3 templates and 1 script for evaluating via purposeful verification and assessing the IP-core nice, discovering and documenting defects.
  • Synthesis: includes 5 actions,  9 artifacts, 3 templates and two scripts for doing the RTL and logical synthesis for acquiring a net-record in accordance a given expertise library.
  • Prototyping: contains 8 activities, 5 artifacts, 1 template and 1 script for prototyping the IP-core within the FPGA, in response to the implementation add-ons.
  • test:: contains 5 activities, 10 artifacts, 4 templates and scripts for generates a internet-record with test structure and look at various-vectors.
  • lower back-end: contains 7 activities, 8 artifacts, 1 template and 1 script for producing the design and encapsulating of the IP-core.
  • additionally there are 3 disciplines that support first-class assurance and infra-structure assist:

  • Deployment,
  • exceptional Assurance
  • Configuration & change management.
  • For these disciplines greater 28 actions, 29 artifacts, and 19 templates had been defined for assisting the deployment of the IP-core as neatly activities for guaranteeing the IP-core high-quality.

    This paper focuses on the movement for aiding ASIC design with the construction of three newer manner disciplines: Synthesis, examine and returned-conclusion, which can be unique described in the subsequent sections.

    three.1    SYNTHESIS self-discipline

    The Synthesis discipline groups the activities to operate Behavioral Synthesis and Logical Synthesis. These activities are responsibility of the Synthesis dressmaker and the Synthesis Engineer as proven in the determine 4.

    The Synthesis fashion designer is responsible for setting up the Synthesis Plan. This plan describes all the planning for the synthesis activities like the technology, tools and ambiance, design constraints, and the order that the components of the device might be synthesized.

    To improve this artifact, the Synthesis clothier must thoughtful design choices taken in previous elements of the design building, just like the non-purposeful necessities that may still be described on the necessities Specification.

    figure four. The Synthesis discipline.

     once the Synthesis Plan has been described, the Synthesis Engineer can operate the activities to complicated the synthesis. These actions are grouped in the following disciplines Workflows:

  • perform Behavioral Synthesis – suggests the actions to convert a behavioral description of the IP-core elaborated on the Implementation self-discipline in a RTL description;
  • function Logical Synthesis - suggests the activities to converts a RTL description elaborated in a net-record description;
  • Optimize Synthesis – answerable for optimizing the actions performed in the old outlined disciplines workflows (operate Behavioral Synthesis and perform Logical Synthesis) to be able to fulfill the IP-core constraints described within the Synthesis Plan;
  • trap Verification components – its main goal is to neighborhood within the Verification component artifact all of the info and directories that makes it possible for the Verification.
  • three.2    examine discipline

    The look at various discipline groups the activities to include Design for Testability (DFT) on the IP-core. These activities are accountability of the verify designer and the test Engineer as shown within the figure 5.

    The check clothier is answerable for constructing the test Plan. This plan describes the entire planning for the look at various activities such as the forms of check structures to be insert in the circuit, the constraints (that will also be extra bendy that these ones to the Logical Synthesis) and the minimal verify coverage suited.

    figure 5. look at various self-discipline.

     once the test Plan has been described, the check Engineer can perform the actions to operate the look at various. These actions are grouped in here Workflows:

  • Insert test structures – shows the actions to converts a netlist description in a netlist with structures to permit DFT;
  • outline test Vectors – shows the activities to outline the test vectors to operate the check in a manufactured IP-core, inserting the test Vectors on the IP-core netlist, in addition to  for examining its effectivity and performance;
  • Optimize verify - responsible for optimizing the activities performed within the workflow “Insert test buildings” in an effort to obtain the design constraints described on the verify Plan;
  • catch Verification components - its main aim is to neighborhood within the Verification element artifact the entire files and directories that allows the Verification.
  • 3.3    again-conclusion discipline

    The back-conclusion discipline groups the activities to generate the layout of the IP-core. These actions are responsibility of the again-end clothier and the back-end Engineer, as proven in the figure 6.

    The lower back-conclusion dressmaker is chargeable for setting up the back-conclusion Plan. This plan describes all the planning for the lower back-end actions such as the localization and the kind of the IO PADs, the constraints and the kind of verification that have to be carried out all over the Validate recreation. 

    figure 6. returned-end discipline.

    as soon as the again-conclusion Plan has been described, the lower back-conclusion Engineer can operate the actions to tricky the lower back-end. These activities are grouped on the following Workflows:

  • operate Floorplanning – the goal of this workflow is to minimize the chip enviornment and delay issues;
  • perform Placement – it is the workflow recreation to location the actual cells, devoid of overlap, with the purpose to minimize the connections measurement;
  • operate Routing – routing is the stage of physical synthesis which is accountable for outlining the metallic routes and levels;
  • Validate design – the circuit design has been synthesized, it's necessary to perform some verification to validate its correctness;
  • operate Packaging – the packaging is liable to locate the chips in tablets that allow the I/O electrical contacts of integrated circuits to be linked in a conventional circuit board;
  • catch Verification add-ons - its main intention is to neighborhood within the Verification element artifact all of the data and directories that makes it possible for the Verification.

    table 2 shows how the ipPROCESS strategy is compliant with DO-254 certification for essential techniques. The table includes all artifacts that are required for the DO-254 certification and the artifacts that the ipPROCESS provides.

    table 2. DO-254 x ipPROCESS.

    DO-254 ipProcess Hardware Plans Plan for HW aspects of Certification (PHAC) instance ipPROCESS Hardware Design Plan Implementation Plan, Verification Plan, Synthesis Plan, examine Plan, back-end Plan HW Verification Plan Verification Plan HW Configuration management Plan Configuration administration Plan Hardware process Assurance Plan example for assurance great Hardware Design information Hardware necessitiesRequirements Specification Hardware Design illustration statistics unique Design statistics Design doc accurate-degree Drawing Design modelassembly Drawings Deployment brandInstallation control Drawings IP-core abstract, user guide Validation And Verification records Hardware Traceability statistics Traceability Matrix Hardware Configuration administration data Hardware Configuration giftsHardware process Assurance facts Hardware Configuration itemsHW Accomplishment abstractipPROCESS instance document

    The PHAC, Hardware system Plan and Hardware Accomplishment summary files are directly linked with the DO-254 certification and are beneath the responsibility of the quality Assurance ipPROCESS self-discipline.

    This evaluation indicates that the ipPROCESS can also be used for airborne projects that intended reap the DO-254 certification, covering 100% of the necessary artifacts.  

    5. results

    To validate the proposed ipPROCESS unencumber, a liquid crystal display Controller has been designed from the necessities until the design synthesis.

    The lcd controller IP-core implements all functionalities of an alphanumeric screen liquid crystal display. It prints 32 characters in two lines, sixteen in every, and possesses a couple of functions to govern the published persona. some of its functionalities are to clear screen, to come back domestic, to entry mode set, cursor or display shift, to put in writing characters, reveal On/Off handle. The block diagram for the lcd Controller can also be viewed in figure 7. 

    figure 7. liquid crystal display Controller architecture.

    The last design of the lcd Controller may also be considered in figure 8. table 3 indicates the most crucial design results.

    table three. IP-core consequences.

    information count number good judgment gate count ~ 10000 Transistors ~ 105500 Silicon enviornment ~ 14 mm²

    figure 8. lcd Controller layout.

    in the first effort for design the liquid crystal display controller, an older version of the ipPROCESS has been used, that didn't consist of the disciplines for directing synthesis, check and lower back-end activities. throughout this tentative a crew of two undergraduate college students have worked for four months and they didn't have success considering the fact that the layout had not satisfied the DRC suggestions.

    within the 2d effort for design the design of the liquid crystal display controller, the proposed version of the ipPROCESS has been used for directing the synthesis, examine and back-end activities. The design has been successfully executed and a group of two undergraduate college students have completed the design in two months.

    When evaluating the design the usage of the proposed ipPROCESS version for doing synthesis, verify and back-end developed with the proposed methodology has a reduce of 50% of the design time to reap a final IP-core design without any violations. moreover, the IP-core designed using the edition of the ipPROCESS is improved documented improving the verbal exchange among designers.


    in this paper, it was introduced the extension of the building method, the ipPROCESS, to consist of also the movement for tough-IP cores construction. This extension contains 3 new disciplines: Synthesis, look at various and returned-end, which have a complete of forty two new activities, under the responsibility of 6 new roles and producing 27 new procedure artifacts. All commercial and army avionics techniques which are prototyped in ASIC or FPGA must be grievance with the DO-254. The ipPROCESS is a technique that supports the design of IP-cores (ASIC and FPGA) in response to the DO-254 common, with an optimized design time. depending of the reassurance degree, it will also be adopted a unique ipPROCESS illustration that covers the standard desires aspects.

    The assignment developed for the lcd with a version the use of the ipPROCESS and a edition with out using the ipPROCESS display that, for teams with out adventure, using the ipPROCESS can results now not best in high quality IP-cores, however lessen the undertaking development time as well.


    [1]    IBM. IBM Rational Unified technique. In ftp://ftp.application.ibm.com/software/rational/web/datasheets/RUP_DS.pdf. Retrieved 22 January 2009.

    [2]    Krebs, Jochen (IBM). "The value of RUP certification". 2007.

    [3]    eXtrem Programming group. intense Programming. In http://www.extremeprogramming.org. Retrieved 22 Janyary 2009.

    [4]    Ken Auer and Roy Miller, severe Programming applied: taking part in to Win, Addison-Wesley, 2002.

    [5]    Fowler, Martin. Chrysler complete Compensation task. In: <http://www.martinfowler.com/bliki/C3.html>. Retrieved August 2009

    [6]    RTCA. Design Assurance counsel for Airborne digital Hardware. 2000, eighty five p.

    [7]    ipPROCESS, “The ipPROCESS Definition”, LINCS, 2006. |on-line|. attainable:  <ipprocess.lincs.org.br>. Retrieved August 2009.

    [8]    Santos, F.; Aziz, A.; Santos, D.; Almeida, M.; Barros, E.. ipProcess: A usage of an IP-core construction method to obtain Time-to-Market and first-rate Assurance in a Multi project ambiance. In Proc. Of the IP/SoC, 2008.


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